International Journal of Research in Signal Processing, Computing & Communication System Design

D. R. V. A. Sharath Kumar ¹, J. Nageswara Reddy ², A. Dileep ²

Affiliations
1 Department of ECE, St. Martins Engineering College, Hyderabad, Telangana, IN
2 Department of ECE, CMR College of Engineering & Technology, Hyderabad, Telangana, IN

Abstract

Phase-Locked Loop, an electronic circuit that controls an oscillator so that it maintains a constant phase angle (i.e., lock) on the frequency of an input, or reference signal. A PLL ensures that a communication signal is locked on a specific frequency and can also be used to generate, modulate and demodulate a signal and divide a frequency. PLL is used often in wireless communications where the oscillator is usually at the receiver and the input signal is extracted from the signal received from the remote transmitter. Design a low power fast-locking PLL by reducing delay and power consumption in gpdk 45nm technology using cadence virtuoso environment. For this purpose, we have designed various individual blocks of PLL by taking into consideration various parameters and simulated. The various blocks are Phase Frequency Detector (PFD), Charge Pump, Loop Filter, Current starved Voltage Controlled Oscillator CSVCO) and Frequency Divider (FD). Here current starved voltage controlled oscillator have been considered for superior performance in form of low power consumption and wide tunable frequency range. The simulation is carried out in the Spectra simulator. The simulation results of PLL and its blocks are reported in this work. It is found that the designed PLL consumes 81.63 uW power from a 1.8V D.C. supply and have a lock time 41.47ns.

Keywords

PLL, PFD, CS-VCO, Concepts of Lock Range, Lock Time, Jitter, Dead zone and Passive Low Pass Filters.

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